Method and device to execute two instruction sequences in an order determined in advance

ABSTRACT

A data processing system executes two instruction sequences in an order determined in advance. Each sequence is stored in a separate memory. Data information used in the second sequence is not guaranteed to be independent of data information used in the first sequence. Increased data handling capacity is achieved in the following manner: both sequences are initially executed in parallel. An address included in a read instruction associated with the second sequence is intermediately stored in an auxiliary memory if it has not been previously selected in conjunction with a write instruction of the second sequence. The intermediately stored address is compared with the write addresses of the first sequence and execution of the second sequence is restarted upon detection of a match.

FIELD OF THE INVENTION

The present invention relates to a method and a device to execute twoinstruction sequences in an order determined in advance, the executionof the first and the second sequence, respectively, including selectionof read instructions each containing its read address for retrieval ofdata information stored in one of a plurality of memory locations eachaccessible by its address in a first and a second separate memoryrespectively, as well as selection of write instructions each containingits write address and data information for transfering this datainformation to a separate memory location assigned to the respectivesequence and accessible by the write address, the separate memorylocations of the sequences being mutually updated with regard to theorder and with regard to the selected write instructions, and the datainformation used in conjunction with the execution of the sequence whichis second due to the order not being guaranteed in advance independentof the data information obtained in conjunction with the execution ofthe sequence which is first due to the order.

DESCRIPTION OF THE RELATED ART

A trivial, conventional solution of the above mentioned informationhandling problem resides in that the execution of the second sequence,is not started until the execution of the first sequence, is terminated.This trivial solution is obtained as a natural necessity in a dataprocessing system controlled by a single processor such that thesequences are executed one at a time using main memory locations commonto both sequences.

It is known to increase data processing capacity by parallel executionof the instruction sequences. As long as the sequences are guaranteed inadvance to be mutually independent, fault-free parallel operation isachieved with the aid of so-called pre-processing or multi-processing,or also with the aid of a one-processor processor system which includesat least two data processing units, each of which executes itsinstruction sequence. It is known to realise information handling bothby means of a main memory which is common to a plurality of dataprocessing units and by means of a plurality of separate memories eachassociated with its data processing unit and mutually updated from timeto time.

When there are sensitive instruction sequences which affect each other,and which must therefore be executed in a prescribed order, there isused e.g. according to the journal "Computer Design", Aug. 15, 1985, pp76-81" or "Balance 8000 System Technical Summary, Sequent ComputerSystems, Inc" programming languages, compilators and sequence hardwarefor parallel processing of mutually independent sequences while parallelprocessing of the sensitive sequences is prevented.

SUMMARY OF THE INVENTION

As already mentioned in the introduction, the present invention relatesto data information processing using two separate memories, eachassigned to one sequence. In the proposed information processing, bothsequences are executed in parallel without regard to the orderdetermined in advance. The dependence of the second sequence on thefirst sequence is monitored and the prescribed order is achieved withthe aid of an intermiediate storage unit which includes an auxiliarymemory and at least one comparison circuit.

Addresses obtained due to read instructions selected during execution ofthe second sequence are intermediately stored in the auxiliary memory.Every write address selected during the execution of the first sequenceis compared with each of the read addresses stored in the auxiliarymemory. As long as no duplication of address is determined, no datainformation dependent on data information obtained during the executionof the first sequence is used during the execution of the secondsequence. If it occurs during execution of the second sequence thatinformation has been retrieved from the separate memory locationassociated with the second sequence, and this information is thencorrected by a write operation associated with the first sequence, i.e.if the two sequences are no longer mutually independent, the auxiliarymemory is erased and the instruction selections of the second sequenceare started once again. Restarting execution of the second sequence thentakes place at a time when a first part of the first sequence is alreadyexecuted, and consequently there is less risk of the second sequencebeing dependent on the remaining part of the first sequence.

Write addresses and data information obtained on the basis of writeinstructions selected during execution of the second sequence are alsostored in the auxiliary memory for facilitating updating of the separatememory associated with the first sequence.

In using the proposed information handling there is obtained an increasein the data processing capacity, if the execution of the second sequenceis independent of at least the instructions selected at the executiontermination of the first sequence. The increased capacity is furtherimproved if a selected address is intermediately stored as a readaddress in the auxiliary memory solely if this address has not beenpresent as a write address earlier during execution of the secondsequence, and is further improved if the separate memory assigned to thesecond sequence is updated in steps in conjunction with every writeinstruction selected during the execution of the first sequence.

The characterizing features of the invention are apparent from theclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described in detail below and with referenceto the accompanying drawing.

FIG. 1 illustrates two data processing units which are each connected toits separate memory and an updating unit.

FIG. 2 illustrates in more detail than FIG. 1 the activation of aseparate memory for reading, writing and updating, as well as aninstruction memory device, and a circuit for starting and identifying,which are included in a data processing unit.

FIG. 3 illustrates an intermediate storage unit included in a dataprocessing unit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A data processing system according to FIG. 1 includes two separatememories 1 for storing data information, which is processed by at leasttwo data processing units 2, which are each connected to its separatememory. Each of the data processing units executes an instructionsequence for controlling assigned functional units (not illustrated inFIG. 1) in carrying out assigned system functions. Depending on whetherthe data processing units are controlled by a common processor orwhether each unit includes a plurality of processors, there isconventionally obtained in principle a one- or multiprocessor system inwhich the instruction sequences are executed, to start with, by means ofthe separate memory of the local sequence, in which system however eachdata processing unit orders an updating unit 3 to update the remainingseparate memories of the system with regard to the order and to theexecuted write instructions. Such a data processing system including aplurality of data processing units and associated separate memorieswhich are mutually updated from time to time, is described in the art,e.g. in S-E Granberg's article "APZ 150: A multiprocessor system for thecontrol of transit telephone exchanges" published in 1976 by InfotechInternational Ltd, Nicholson House, Maidenhead, Berkshire, England.

FIG. 1 illustrates in a greatly simplified way, taking into account thepresent invention, two data processing units 2 for executing the abovementioned first and second instruction sequences in an order determinedin advance. Apart from a conventional instruction memory device 4 forselecting, one at a time, instructions stored in an instruction memory,each data processing unit includes a start/identifying circuit 5, forstating whether its own sequence is the first independent or the secondpossibly dependent sequence, and an intermediate storage unit 6. Withthe aid of the intermediate storage units, the data processing units 2control the updating of the separate memories, and thereby the executionof the sequences in the order determined in advance. The intermediatestorage unit, the data processing unit of which executes the secondsequence, intermediately stores addresses included in the instructionsand thus monitors the dependence of the second sequence on the firstsequence.

It is indicated that data information is transferred partly due to writeinstructions from the instruction memory devices to the associatedseparate memories, and partly due to read instructions from the separatememories to the associated data processing units.

The start/identifying circuits 5 of the data processing units are eachprovided with a starting signal output 7 which is connected to astarting signal input 8 of the other circuit 5. There is thus indicatedthe possibility of executing both sequences in parallel, that isdescribed hereinafter and used in the proposed information handling.

The start/identifying circuits 5 are each provided with an identifyingsignal output 9, which is connected to a first identifying signal input10 on the intermediate storage unit 6 of the other data processing unit.The intermediate storage unit of each of the data processing units isprovided with an address input 11 and a write marking input 12 forreceiving write addresses selected from the instruction memory device 4of the other data processing unit. The intermediate storage units 6 aremutually connected via an updating output 13 and an updating input 14.

FIG. 2 illustrates in more detail than FIG. 1 some data processing unitdetails, knowledge of which is required for understanding the proposedinformation handling.

The instruction memory device 4 includes an instruction memory 15 forstoring an instruction sequence, which is read out with the aid of aselection device 16 from the instruction memory, one instruction at atime, due to activation by one of the selection device outputs.

The sequence includes three instruction types. The first type,hereinafter designated "read instruction", which is identified by abinary ONE set read bit position 17, is used for ordering the retrievalof data from a location of the separate memory 1 connected to theinstruction memory, access to the separate memory being obtained withthe aid of an address, e.g. A1, stored in a number of address bitpositions 18, the address being included in the read bit markedinstruction. The read bit positions 17 and the address bit positions 18are respectively connected to a read activating input 19 and anaddressing circuit 20 of the separate memory.

The second instruction type, hereinafter designated "write instruction",which is identified by a ONE set write bit position 21, is used forordering that data, e.g. D2, is written into a separate memory location,this data being included in the write bit marked instruction and storedin a number of data bit positions 22, while using an address, e.g. A2,which is also included in the write bit marked instruction and stored inthe address bit positions 18. The write bit positions 21 are connectedto a write activating input 23 of the separate memory.

The third instruction type, which is identified by ZERO set bitpositions 17 and 21, is used for ordering information handling withoutreading from or writing into the separate memory. The use of theinformation, e.g. S1, stored in the bit positions 18 and 22, which areassociated with a third type of instruction, are not within the scope ofthe invention, but FIG. 2 illustrates a first OR gate 24, with itsinputs connected to the bit positions 17 and 21 and its output connectedto an inverting activating input of a first AND gate device 25, which inan activated state transfers the contents, e.g. S1, of the bit positions18 and 22 directly to the data processing unit.

The start/identifying circuits 5 of the data processing units eachinclude second and third OR gates 26 and 27, according to FIG. 2. Gate26 has one of its inputs connected to the output of the gate 27, theinputs of which are connected to the above-mentioned starting signalinput 8 and to a restarting signal output 28 of the intermediate storageunit 6 included in the same data processing unit. The data processingunits each include a starting signal generator, not illustrated in FIG.2, the output of which is connected via a starting terminal 29 to theother input of gate 26, to the above-mentioned starting signal output 7and to the setting input of a first flipflop 30, with an outputconstituting the above-mentioned identifying signal output 9 which isconnected to a second identifying signal input 31 on the localintermediate storage unit 6. A second flipflop 32 has its setting inputconnected to the output of gate 27 and its output connected to a thirdidentifying signal input 33 on the local intermediate storage unit 6. Inits activated state the gate 26 selects an instruction of the thirdtype, which is a starting instruction with the contents S1, due to whichthe data processing unit starts the associated instruction sequenceexecution with the aid of its selection device 16. It is assumed thatthe sequence stored in the instruction memory 15 is terminated inconjunction with the activation of a selection device output 34, whichis connected to the resetting inputs of the flipflops 30 and 32.

Execution of the first sequence is started by the local starting signalgenerator. Consequently, a binary ONE on the output of the firstflipflop 30 indicates that the instruction selections associated withthe local sequence are in progress and that the local sequence is thefirst sequence. A binary ONE on the output of the second flipflop 32indicates that the instruction selections associated with the localsequence are in progress and that the local sequence is the secondsequence. In accordance with the invention, the instructions of bothsequences are selected in parallel, which is achieved e.g. by a startingsignal transfer from the starting signal output 7 associated with thefirst sequence to the starting signal input 8 associated with the secondsequence.

The read addresses and write addresses selected from the instructionmemory 15 are transferred via terminals 35-37 to the intermediate memoryunit 6 of the data processsing unit. FIG. 2 illustrates theabove-mentioned identifying signal input 10 and write address inputs11-12 of the intermediate storage unit, and a first control terminal 38,which is connected to the output of the first OR gate 24.

Finally, conventional updating functions are indicated in FIG. 2 withthe aid of dashed communication lines. The updating unit 3 is providedwith order terminals 39 and 40. Updating order signals and updatingaddresses are sent in parallel via the terminals 39 and 40,respectively. Due to an updating order obtained from one of theintermediate storage units, the updating unit transfers the order signalto the local separate memory read activating input 19 and to the writeactivating input 23 of the other separate memory, and the updating unittransfers the address associated with the updating order to theaddressing circuits 20 of the separate memories. There is thus obtaineda data transfer from the local separate memory via the updating unit tothe other separate memory.

FIG. 3 illustrates an intermediate storage unit which includes anauxiliary memory 41. The latter has columns for intermediate-storing ofread addresses and write addresses transferred via the terminals 35-37,the columns being selected for writing, reading and erasure with the aidof a scanning device 42. It will be later described how the auxiliarymemory is erased when the associated instruction sequence is finallyexecuted.

The front edge of a scanning pulse sent from a fourth OR gate 43 setsthe scanning device to zero. Access to the auxiliary memory columns isobtained by the front edges of stepping pulses which are generated by astepping generator 44 and transferred via an activated stepping AND gate45 to a stepping terminal 46 of the scanning device. The stepping pulsesare also sent to a read activating terminal 47, resulting in the columncontents being read one at a time.

The intermediate storage unit according to FIG. 3 includes a first NORgate 48, with its inputs adapted for receiving the write markings andread markings intermediately stored in write bit positions 19 and readbit positions 50 of the auxiliary memory, and with its inverting outputconnected via a stop OR gate 51 to an inverting input of the steppingAND gate 45 and to first inputs of a first and a second AND control gate52 and 53, the outputs of which are connected to the OR gate 43. Thecontrol gate 52 has its second input connected to a third AND controlgate 54, the inputs of which are connected to the above mentionedidentifying signal input 33 and control terminal 38.

Consequently, scanning pulses are only generated in the intermediatestorage unit included in the data processing unit executing the secondsequence. A scanning operation is ordered upon selection of a readinstruction or a write instruction. A stop in stepping is obtained whenan unoccupied column is read, i.e. a column which is neither writemarked or read marked. A condition for starting scanning is that thepreceding stepping has been stopped.

The first NOR gate 48 is connected to a write activating input 55 of thescanning device. It is assumed that a write instruction with associatedaddress A3 and a read instruction with associated address A4 constitutethe first and second instructions of the second sequence directedtowards the associated separate memory, the write/read addresses ofthese instructions being intermediately stored in the described way inthe first and second columns of the auxiliary memory, these columnshaving bit positions 49 and 50, which were set to zero prior torespective storage.

The control gate 53 has its second input connected to a fourth ANDcontrol gate 56, with the first input connected to the above-mentionedfirst identifying input 10, and with the second input connected via theabove mentioned write marking input 12 to the write bit positions 21 inthe instruction memory 15 which stores the first sequence. A scanningoperation is thus also ordered for the second sequence intermediatestorage unit upon selecting a write instruction associated with thefirst sequence. The timing frequency of the stepping generator 44 isassumed to be sufficiently high in relation to the instruction selectionspeed that all the scanning operations ordered via the control gates 54and 56 have time to be carried out.

The intermediate storage unit includes a first comparison circuit 57,the output of which is activated when the address obtained via terminal37 from the instruction memory 15 is the same as one of the addressesread from the auxiliary memory address bit positions 58 during ascanning operation. A fifth AND control gate 59 has its output connectedto stop OR gate 51, its first input connected to comparison circuit 57and its second input disposed for receiving the write markingsintermediately stored in the auxiliary memory write bit positions 49.There is thus obtained that a scanning operation is stopped if a readaddress or write address selected from the instruction memory agreeswith an intermediately stored write address.

It is assumed that the selection of the read instruction with associatedaddress A4 is repeated a first time after selection of a number ofinstructions (not illustrated in FIG. 3) with addresses other than A3and A4. There is obtained that the selection repeated a first time doesnot result in a scanning stop due to address duplication determined bythe first comparison circuit 57, so that the read instruction repeated afirst time is intermediately stored a second time in a column whose bitpositions 49 and 50 were previously set to ZERO. The second sequenceread instructions with associated address Ax are called first categoryinstructions if they are selected before the same address Ax is presentin the second sequence in conjunction with the selection of a writeinstruction.

It is assumed that a write instruction with associated address A4 isselected after selection of the above mentioned read instruction isrepeated for the first time and after selection of a number ofinstructions (not illustrated in FIG. 3) with addresses other than A3and A4. There is thus obtained that this write instruction isintermediately stored in a previously unoccupied column. It is furtherassumed that selection of the read instruction with associated addressA4 is repeated a second time after selection of the mentioned writeinstruction with the address A4. There is obtained a scanning stop inconjunction upon reading the intermediately stored write instructionwith the address A4, but no read marking is carried out in bit position50. The read instruction with associated address A4 repeated a secondtime constitutes a second category instruction, whose associated addressis not intermediately stored in the auxiliary memory.

The intermediate storage unit of one of the data processing unitsincludes a second comparison circuit 60, the output of which isactivated on duplication between the address transferred via theabove-mentioned address input 11, this address being selected from theaddress bit positions 18 included in the instruction memory 15 of theother data processing unit, and one of the addresses read from theaddress bit positions 58 of the auxiliary memory during a scanningoperation. The second comparison circuit is connected to the first inputof a sixth AND control gate 61, the second input of which is connectedto the above-mentioned control gate 56, and the output of which isconnected to a first input of a seventh AND control gate 62. The outputof the control gate 62 which receives on its second input the readmarkings intermediately stored in the auxiliary memory bit positions 50,constitutes the above-mentioned restarting signal output 28 and isconnected to an erase OR gate 63. The OR gate 27 illustrated in FIG. 2receives a restarting signal from an activated control gate 62. Thescanning device 42 receives from an activated erase OR gate 63 anerasure order pulse, due to which all address information intermediatelystored in the auxiliary memory is immediately cancelled.

There is obtained that an erasure of the auxilary memory and a restartof the execution of the second sequence is carried out if aintermediately stored first category read instruction is encountered,where the associated address of this instruction agrees with the addressassociated with a write instruction which is selected during theexecution of the first sequence. The erasure is required since theassociated data processing unit has received data information from itsseparate memory due to the encountered first category instruction whichthe memory would not have received if attention had been consistentlypaid to the order determined in advance, i.e. if instructions in thefirst and second sequences had not been selected in parallel.

The intermediate storage unit includes a second NOR gate 64 with inputsconnected to the above-mentioned identifying signal inputs 10 and 33 andwith an inverting output connected to the OR gate 43. When theselections of the first and the second sequences are terminated, ascanning operation is consequently ordered, although the scanning iswithout result in the intermediate storage unit included in the dataprocessing unit which has executed the first sequence. An eighth ANDcontrol gate 65 has its inputs connected to the NOR gates 48 and 64 andits output connected to erase OR gate 63. An erase order pulse isobtained when the scanning operation started by the NOR gate 64 isterminated.

During the last mentioned scanning operation the second sequenceintermediate storage unit generates updating information which comprisesall write addresses selected and intermediately stored during executionof the second sequence. The write markings read from the auxiliarymemory bit positions 49 are received by a ninth AND control gate 66which has its second input connected to NOR gate 64 and its outputconnected via an updating OR gate 67 to the above mentioned orderterminal 39 of the updating unit 3. The updating addresses read from theauxiliary memory address bit positions 58 are transferred with the aidof a second AND gate device 68 which has its activating input connectedto the output of the control gate 66, via an OR gate device 69, to theabove mentioned order terminal 40 of the updating unit 3.

A tenth AND control gate 70 with its first input receiving the writemarkings intermediately stored in the bit positions 49 of the auxiliarymemory has its second input connected to the output of the control gate61 and its output constituting the above-mentioned updating output 13connected to a third input of the stop OR gate 51. There is obtainedthat the scanning operation started by the activation of control gate 56is stopped if duplication is determined by the second comparison circuit60 between a write address selected during execution of the firstsequence and one of the write addresses intermediate-stored in theauxiliary memory during execution of the second sequence.

The intermediate storage unit illustrated in FIG. 3 finally includes aneleventh AND control gate 71 which has its first input connected to theabove-mentioned identifying signal input 31, and has its second inputbeing activated by the rear flank of a pulse connected to the terminal36, and has its third input being inverting and constituting theabove-mentioned updating input 14, and which has its output connected tothe updating OR gate 67 and to the activating input of a third AND gatedevice 72 with its input connected to the intermediate storage unitterminal 37 and its output connected to the OR gate device 69. The ORgate 67 and the OR gate device 69 of the intermediate storage unitassigned to the first sequence consquently transfer as updatinginformation a write address selected during the execution of the firstsequence and included in this sequence, unless this write address isintermediately stored in the auxiliary memory assigned to the secondsequence.

For example, if data are written into a separate memory locationaccessible by the address A3 and assigned to the first sequence, itwould be wrong then to update the second sequence separate memory since,according to what has been assumed above, this write address A3 haspreviously been intermediately stored in the second sequence auxiliarymemory. On the other hand, if it is a question of updating due to awrite instruction with the address A4 included in the first sequence,and if it has been assumed according to the above that this adress A4has previously been intermediately stored in the second sequenceauxiliary memory, partly as associated with a first category readinstruction and partly as associated with a write instruction, then thecontents of the auxiliary memory are erased when the read address A4 isencountered. The control gate 70 of the second sequence intermediatestorage unit is therefore not activated, so that correct updating, inthe manner described above, of the second sequence separate memory iscarried out with the aid of the control gate 71 of the first sequenceintermediate storage unit and while using the address A4.

According to a method for intermediately storing and updating notillustrated on the drawing, the first sequence write addresses and thesecond sequence write instructions, i.e. write addresses and associateddata information, are intermediately stored in the respective auxiliarymemory. The comparison between each of the intermediately stored writeaddresses associated with the first sequence and each of theintermediately stored read addresses associated with the second sequenceis carried out in parallel with updating of the second sequence separatememory when the first sequence instruction selections are terminated,restarting of the second sequence execution being ordered due to addressduplication determined on comparison. The updating of the separatememory associated with the first sequence is carried out with the aid ofthe intermediately write instructions associated with the secondsequence when the second sequence instruction selection are terminated.

With the aid of the last-mentioned method for intermediately storing andupdating, there is obtained an increase in the data processing capacityby means of the proposed execution of both sequences in parallel only ifexecution of the second sequence does not have to be restarted.

As an overall effect, there is achieved with the aid of theintermediate-storage units of the data processing units that the firstand the second sequences are finally executed fault-free in the orderdetermined in advance, in spite of the execution of both sequenceshaving been initally ordered to be carried out in parallel.

We claim:
 1. A method of operating computer means to enable the computermeans to execute a first and a second instruction sequence, saidcomputer means comprising an auxiliary memory means and a first andsecond memory for storing the first and second instruction sequences,each memory comprising a plurality of memory locations accessible by anaddress, execution of the first and second sequences including selectionof at least one read instruction and selection of at least one writeinstruction, said at least one read instruction comprising a readaddress for retrieval of data stored in one of said memory locationseach accessible by its address in said first and second memories,respectively, and said at least one write instruction comprising a writeaddress and data, said write address specifying a memory location towhich the data is to be transferred, wherein data used in conjunctionwith the execution of the second sequence is not necessarily independentof data obtained in conjunction with the execution of the firstsequence, said method comprising the steps of:executing instructions inboth sequences independent of a predetermined order of execution of thesequences; upon encountering a read instruction during the execution ofthe second sequence, storing the read address of said read instructionencountered during the execution of the second sequence in saidauxiliary memory means, if this address has not previously been selectedin conjunction with execution of a write instruction in the secondsequence; upon encountering a write instruction during the execution ofthe first sequence, comparing each read address stored in said auxiliarymemory means and the address of said write instruction encounteredduring the execution of the first sequence; and re-executing theinstructions in the second sequence responsive to the comparing step ifthe address of said write instruction encountered during the executionof the first sequence is any read address stored in said auxiliarymemory means.
 2. A method according to claim 1, further comprising thesteps of:upon encountering a write instruction during the execution ofthe second sequence, storing the write address of said write instructionin said auxiliary memory means; upon encountering a write instructionduring the execution of the first sequence, comparing each write addressstored in said auxiliary memory means and the write address of saidwrite instruction encountered during the execution of the firstsequence; updating contents of said memory locations of the secondmemory in conjunction with every execution of a write instruction in thefirst sequence responsive to the step of comparing the write addresses,if the write address of said write instruction encountered during theexecution of the first sequence is not equal to any write address storedin said auxiliary memory means; and preventing an updating of saidmemory locations of the second memory responsive to the step ofcomparing each write address, if the write address of said writeinstruction encountered during the execution of the first sequence isequal to any write address stored in said auxiliary memory means.
 3. Anapparatus for executing a first and second instruction sequence, each ofthe first and second instruction sequences comprising at least oneinstruction, said first sequence being logically executable before saidsecond sequence, wherein data used in conjunction with execution of saidsecond sequence is not necessarily independent of data used inconjunction with the execution of said first sequence said apparatuscomprising:a first starting circuit for starting execution of said firstsequence; first and second instruction memory means for storinginstructions of said first and second instruction sequences,respectively, and for selecting the stored instructions one at a time,said stored instructions comprising at least one read instruction and atleast one write instruction; first and second separate memory meansconnected to said first and second instruction memory means,respectively, and having at least one memory location for storing datato be read and written using read/write addresses selected fromread/write address bit positions in the first and second instructionmemory means; updating means for updating contents of said at least onememory location of said first and second separate memory meansresponsive to a logical order of execution of the first and secondinstruction sequences and to selected write instructions; a secondstarting circuit for starting execution of said second sequence, saidsecond starting circuit having a first activating input connected tosaid first starting circuit and a second activating input; auxiliarymemory means comprising an input connected to said second instructionmemory means, read address bit positions, means for identifying memoryaddresses accesses by the write instruction of said second sequence,means for determining whether memory addresses have previously beenselected by the execution of a write instruction of said secondsequence, and storing means responsive to said determining means forstoring in said auxiliary memory means at least one address obtainedfrom a read instruction selected during execution of said secondsequence when said at least one address is not one of the memoryaddresses determined by said determining means to have been selected bythe execution of the write instruction of said second sequence;comparing means for comparing two addresses, said means comprising atleast one first comparison terminal connected to write address bitpositions of said first instruction memory means for receiving the writeaddresses of the instructions of said first sequence, at least onesecond comparison terminal connected to read address bit positions ofsaid auxiliary memory means for receiving the read addresses of theinstructions of said second sequence stored therin, and an output foroutputting a restart signal when said read address received at the atleast one second comparison terminal is equal to any said write addressreceived at the at least one first comparison terminal, said outputconnected to said second activating input of said second startingcircuit for activating said second starting circuit to re-execute theinstructions in said second sequence responsive to outputting saidrestart signal.
 4. The apparatus according to claim 3, wherein saidauxiliary memory means comprises write address bit positions forintermediately storing at least one address which was obtained from atleast one write instruction selected during execution of said secondsequence, said apparatus further comprising:an updating comparisoncircuit comprising at least one first comparison terminal connected tothe write address bit positions of said first instruction memory means,at least one second comparison terminal connected to said write addressbit positions of said auxiliary memory means, and an output foroutputting a first logical updating signal when the addresses receivedon said at least one first comparison terminal are unequal to theaddresses received on said at least one second comparison terminal andfor outputting a second logical updating signal when the addressesreceived on said at least one first comparison terminal are equal to theaddresses received on said at least one second comparison terminal; andan updating control circuit which is activated and de-activated uponreceiving, respectively, said first and said second logical updatingsignal, said control circuit comprising at least one input terminalconnected to the write address bit positions of said first instructionmemory means, and at least one output terminal connected to saidupdating means.
 5. A method of operating a computer to enable thecomputer to execute a first and second instruction sequence, eachinstruction sequence having at least one read instruction and at leastone write instruction, the at least one read and the at least one writeinstruction comprising an address and data, wherein data used inconjunction with execution of the second sequence is not necessarilyindependent of data obtained in conjunction with the execution of thefirst sequence, said method comprising the steps of:storing the firstsequence in a first memory in the computer and storing the secondsequence in a second memory in the computer; executing instructions inboth sequences independent of a predetermined order of execution of thesequences; upon encountering a read instruction during the execution ofthe second sequence, storing the address of said read instructionencountered during the execution of the second sequence in a separatememory in the computer, if this address has not previously been selectedin conjunction with execution of a write instruction in the secondsequence; upon encountering a write instruction during the execution ofthe first sequence, comparing each address stored in the separate memoryand the address of said write instruction encountered during theexecution of the first sequence; and re-executing instructions in thesecond sequence responsive to the comparing step if the address of saidwrite instruction encountered during the execution of the first sequenceis equal to any address stored in the separate memory.
 6. A methodaccording to claim 5, further comprising the steps of:upon encounteringa write instruction during the execution of the second sequence, storingthe address of said write instruction in the separate memory; uponencountering a write instruction during the execution of the firstsequence, comparing each address stored in the separate memory and thewrite address of said write instruction encountered during the executionof the first sequence; updating the data stored in the second memory inconjunction with every execution of a write instruction in the firstsequence responsive to the step of comparing each address, if the writeaddress of said write instruction encountered during the execution ofthe first sequence is not equal to any address stored in the separatememory; and preventing an updating of the data stored in the secondmemory responsive to the step of comparing each address, if the writeaddress of said write instruction encountered during the execution ofthe first sequence is equal to an address stored in the separate memory.